# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/renesas,ether.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Renesas Electronics SH EtherMAC

allOf:
  - $ref: ethernet-controller.yaml#

maintainers:
  - Sergei Shtylyov <sergei.shtylyov@gmail.com>

properties:
  compatible:
    oneOf:
      - items:
          - enum:
              - renesas,gether-r8a7740   # device is a part of R8A7740 SoC
              - renesas,gether-r8a77980  # device is a part of R8A77980 SoC
              - renesas,ether-r7s72100   # device is a part of R7S72100 SoC
              - renesas,ether-r7s9210    # device is a part of R7S9210 SoC
      - items:
          - enum:
              - renesas,ether-r8a7778    # device is a part of R8A7778 SoC
              - renesas,ether-r8a7779    # device is a part of R8A7779 SoC
          - enum:
              - renesas,rcar-gen1-ether  # a generic R-Car Gen1 device
      - items:
          - enum:
              - renesas,ether-r8a7742    # device is a part of R8A7742 SoC
              - renesas,ether-r8a7743    # device is a part of R8A7743 SoC
              - renesas,ether-r8a7745    # device is a part of R8A7745 SoC
              - renesas,ether-r8a7790    # device is a part of R8A7790 SoC
              - renesas,ether-r8a7791    # device is a part of R8A7791 SoC
              - renesas,ether-r8a7793    # device is a part of R8A7793 SoC
              - renesas,ether-r8a7794    # device is a part of R8A7794 SoC
          - enum:
              - renesas,rcar-gen2-ether  # a generic R-Car Gen2 or RZ/G1 device

  reg:
    items:
      - description: E-DMAC/feLic registers
      - description: TSU registers
    minItems: 1

  interrupts:
    maxItems: 1

  '#address-cells':
    description: number of address cells for the MDIO bus
    const: 1

  '#size-cells':
    description: number of size cells on the MDIO bus
    const: 0

  clocks:
    maxItems: 1

  power-domains:
    maxItems: 1

  resets:
    maxItems: 1

  phy-mode: true

  phy-handle: true

  renesas,no-ether-link:
    type: boolean
    description:
      specify when a board does not provide a proper Ether LINK signal

  renesas,ether-link-active-low:
    type: boolean
    description:
      specify when the Ether LINK signal is active-low instead of normal
      active-high

patternProperties:
  "^ethernet-phy@[0-9a-f]$":
    type: object
    $ref: ethernet-phy.yaml#

required:
  - compatible
  - reg
  - interrupts
  - phy-mode
  - phy-handle
  - '#address-cells'
  - '#size-cells'
  - clocks

additionalProperties: false

examples:
  # Lager board
  - |
    #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/power/r8a7790-sysc.h>
    #include <dt-bindings/gpio/gpio.h>

    ethernet@ee700000 {
        compatible = "renesas,ether-r8a7790", "renesas,rcar-gen2-ether";
        reg = <0xee700000 0x400>;
        interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
        clocks = <&cpg CPG_MOD 813>;
        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
        resets = <&cpg 813>;
        phy-mode = "rmii";
        phy-handle = <&phy1>;
        renesas,ether-link-active-low;
        #address-cells = <1>;
        #size-cells = <0>;

        phy1: ethernet-phy@1 {
            compatible = "ethernet-phy-id0022.1537",
                         "ethernet-phy-ieee802.3-c22";
            reg = <1>;
            interrupt-parent = <&irqc0>;
            interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
            micrel,led-mode = <1>;
            reset-gpios = <&gpio5 31 GPIO_ACTIVE_LOW>;
        };
    };
